摘要

 

近几年，随着5G相关应用的大举发力，相关配套产品和生态产品中，NAND Flash频繁亮相。再加上疫情对于市场的影响，使得商家逐渐开始重视数据化企业管理与分析以及企业信息安全，进而导致企业数据中心的建设对NAND Flash的需求也越来越多，但由于种种原因，NAND Flash的国产化并不足。NAND Flash控制器有特殊的系统接口，可以对NAND Flash颗粒进行操作以及对坏块的标记和管理。但NAND Flash颗粒存在的干扰问题，促使控制器需要通过纠错算法来纠正数据错误，同时控制器的I/O性能差距也可以减缓数据的传输速度。

 

本设计采用NB-LDPC码，使用随机构造法构造适用于大容量存储码率为0.89的校验矩阵。在经典大数逻辑译码算法基础上进行改进，以解决先验信息的利用率低的问题。使用对数线性混合量化方法，减小译码误差。同时提出一种新型译码器架构，以解决面积大、资源利用率低的问题。在接口处设计兼容ONFI和Toggle规则。最终设计出一款高吞吐率、类CPU架构、强纠错性能的NB-LDPC混合译码算法NAND Flash控制器。

 

本设计基于TSMC 28nm工艺，利用MATLAB软件进行算法设计仿真，使用Modelsim软件进行控制器的硬件设计与仿真，在FPGA平台下进行仿真测试最楼利用Design compiler工具进行电路的逻辑综合。当误码率小于10-4时，算法编码增益5.5dB。最高可纠错90位随机错误，最高时钟频率200MHz,面积2.25mm2，吞吐率1.41Gb/s。

 

 

 

关键词： 集成电路，NAND Flash，控制器，LDPC码2

 

ABSTRACT

 

In recent years, with the development of 5G related applications,NAND Flash appears frequently in related supporting products and ecological products. In addition to the impact of the epidemic on the market,businesses gradually began to pay attention to data-based enterprise management and analysis and enterprise information security, which led to the construction of enterprise data center and more and more demand for NAND Flash. However, due to various reasons, the localization of NAND Flash is not enough.NAND Flash controller has a special system interface,which can operate NAND Flash particles and mark and manage bad blocks. However, due to the interference problem of NAND Flash particles,the controller needs to correct data errors through error correction algorithm. At the same time, the I/O performance gap of the controller can also slow down the data transmission speed.

 

In this design, NB-LDPC code is used,and random construction method is used to construct a parity check matrix suitable for mass storage with bit rate of 0.89.In order to solve the problem of low utilization of prior information, the classical large number logic decoding algorithm is improved. Log linear hybrid quantization is used to reduce the decoding error.At the same time, a new decoder architecture is proposed tosolve the problems of large area and low resource utilization. The interface is designed to be compatible with ONFI and Toggle rules.Finally, a NAND flash controller with high throughput,CPU like architecture and strong error correction performance is designed.

 

This design is based on TSMC 28nm process,using MATLAB software for algorithm design simulation, using Modelsim software for hardware design and Simulation of the controller, using FPGA platform for simulation test, using design compiler tool for circuit logic synthesis. When the BER is less than 10-4, the coding gain is 5.5dB.It can correct up to 90 bit random errors with a maximum clock frequency of 200MHz, an area of 2.25mm2 and a throughput of 1.41Gb/s.

 

Key Words: Integrated circuit, NAND Flash, Controller, Low density parity check code